In recent years advancements in integrated circuit technology have enabled development of memory chips of greatly increased capacity, reducing the cost per unit for solid state storage devices (SSDs). Because of the cost reductions and the greatly reduced space requirements, SSDs have become increasingly popular as an alternative or supplement to magnetic storage devices such as tapes or disk drives, particularly in I/O bound processing systems. U.S. Pat. No. 4,630,230, issued Dec. 16, 1986, to Sundet, describes an SSD utilizing an organization which minimizes data fan in and fan out and addressing fan out requirements. The storage section is organized into two groups, each group including a plurality of sections. Each section provided includes eight banks, paired in modules. The addressing and data is provided to the two groups identically so that each group receives one word each clock cycle. A pipeline technique of data distribution is employed, where data words are supplied to a first section in each group and transferred section to section on each succeeding clock cycle until all sections have a word and may be written into storage simultaneously. In the case of a write operation, words are captured from the sections simultaneously and passed out of the memory section to section. Refresh operations are accomplished on a periodic basis and a plurality of power supplies are provided for the storage modules in order to distribute refresh current demand over time and between the power supplies, providing for a safe and speedy refresh operation.
U.S. Pat. No. 4,951,246, issued Aug. 21, 1990, to Fromm et al., teaches a nibble-mode dynamic random access memory (DRAM) SSD utilizing the general concept of pipelining as described in U.S. Pat. No. 4,630,230, issued Dec. 16, 1986, to J. Sundet. Memory is organized into sections, with each section including a plurality of groups. Each group is organized into a plurality of ranks, with each rank including a pair of banks. Each group includes addressing circuitry shared between the two banks, each of which may be independently controlled, one at a time. Nibble-mode DRAM is deployed in each bank, and the addressing circuitry is adapted to address the DRAM in Nibble-mode cycles.
A plurality of ports into the SSD are provided, with each port having an independent data path to each section of the memory. Each section includes steering logic to direct data flow from a path into the group being accessed. An assembly register is provided for the group of ranks in a group, and includes a plurality of segments with data storage locations, with one segment for each rank. The assembly register is configured to receive data words in a pipeline fashion, which are in turn transferred from the assembly register into a write data register, which includes a plurality of locations corresponding to the locations in the assembly register. The data words are transferred from the write register into the memory under the control of the addressing circuitry. In a read operation, the ranks are accessed to simultaneously produce a plurality of data words, which are loaded in parallel into a read data register which is configured to pipeline the data to a data path out to a port.
The designers of modern storage devices have a number of requirements which include maximizing the capacity of a device to store data, maximizing the data transfer rate into and out of the device, maximizing reliability, and minimizing cost.
In light of these requirements, there is a need to provide for a fast way of distributing data across individual memory components in a way that prevents multibit uncorrectable or undetectable errors due to the failure of a single memory component.
There is a further need to provide for an easy way of logically replacing a failed memory component.
There is a further need to provide for a way of distributing power comsumption evenly across the device to eliminate the need for special load regulation of the power supply.
There is a further need to provide for a way of eliminating the time required to wait while memory is being refreshed.